PDF) Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique
PDF) Test pattern generation based on arithmetic operations
PDF) Symmetry Measure for Memory Test and Its Application in BIST Optimization
Dimitris Magos's research works | University of West Attica, Athens (TEIATH) and other places
PDF) Test Embedding with Discrete Logarithms
PDF) Survival analysis for modeling critical events that communities may undergo in dynamic social networks
PDF) UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations
PDF) A domain-specific approach for software development on Manycore platforms
PDF) Detection of Delay Faults in Memory Address Decoders
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults
PDF) Efficient Test Compaction for Pseudo-Random Testing
PDF) Detection of Delay Faults in Memory Address Decoders
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
IVML > People > Phivos Mylonas
PDF) Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
Steffen Tarnick's research works | Universität Potsdam, Potsdam and other places
PDF) High-Level Test Synthesis for Delay Fault Testability
PDF) Extending Internet into Space – ESA DTN Testbed Implementation and Evaluation
PDF) Modeling and Simulation of Efficient March Algorithm for Memory Testing
PDF) On the Generation of Functional Test Programs for the Cache Replacement Logic
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
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NiDS2022 (Novel & Intelligent Digital Systems) - ATHENS
PDF) Multimode scan: Test per clock BIST for IP cores
